2024
Abid, Saad Bin; Kosiol, Jens; Mittal, Rakshit; Ober, Iulian; Posse, Ernesto
MoDeVVa’24: Model Driven Engineering, Verification and Validation Proceedings Article
In: Proceedings of 27th International Conference on Model-Driven Engineering Languages and Systems (MODELS '24) : Companion Proceedings, Association for Computing Machinery, Linz, Austria, 2024.
@inproceedings{nokey,
title = {MoDeVVa’24: Model Driven Engineering, Verification and Validation},
author = {Saad Bin Abid and Jens Kosiol and Rakshit Mittal and Iulian Ober and Ernesto Posse},
year = {2024},
date = {2024-10-31},
urldate = {2024-10-31},
booktitle = {Proceedings of 27th International Conference on Model-Driven Engineering Languages and Systems (MODELS '24) : Companion Proceedings},
publisher = {Association for Computing Machinery},
address = {Linz, Austria},
keywords = {},
pubstate = {published},
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Amrani, Moussa; Mittal, Rakshit; Goulão, Miguel; Amaral, Vasco; Guérin, Sylvain; Martinez, Salvador; Blouin, Dominique; Bhobe, Anish; Hallak, Yara
A Survey of Federative Approaches for Model Management in MBSE Workshop
1st Workshop on Model Management (MoM), Proceedings of 27th International Conference on Model-Driven Engineering Languages and Systems (MODELS '24) : Companion Proceedings, Association for Computing Machinery, Linz, Austria, 2024.
Abstract | BibTeX | Altmetric | Dimensions | PlumX | Links:
@workshop{10.1145/3652620.3688221,
title = {A Survey of Federative Approaches for Model Management in MBSE},
author = {Moussa Amrani and Rakshit Mittal and Miguel Goulão and Vasco Amaral and Sylvain Guérin and Salvador Martinez and Dominique Blouin and Anish Bhobe and Yara Hallak},
url = {https://doi.org/10.1145/3652620.3688221},
doi = {10.1145/3652620.3688221},
year = {2024},
date = {2024-08-13},
urldate = {2024-08-13},
booktitle = {1st Workshop on Model Management (MoM), Proceedings of 27th International Conference on Model-Driven Engineering Languages and Systems (MODELS '24) : Companion Proceedings},
publisher = {Association for Computing Machinery},
address = {Linz, Austria},
abstract = {Model-based Systems Engineering (MBSE) advocates the use of models in every stage of development, leading to large number of models that need coordination, collaboration, and discipline management. Model Management (MoM) is a possible approach to manage inter-related collections of models among which Model Federation (MF) provides unique capabilities, like independence of development in individual modelling domains. There is currently a lack of studies about commonalities, variabilities, and gaps in MF approaches. In this paper, we propose a survey and a critical discussion of carefully selected papers about MF. From 59 contributions collected by experts in MoM, we selected, and classified, 23 papers. We extract the main trends we observed, according to our Classification. We then critically review the Classification, and discuss important gaps found in our corpus. The survey results and artefacts are all available online.},
keywords = {},
pubstate = {published},
tppubtype = {workshop}
}
Model-based Systems Engineering (MBSE) advocates the use of models in every stage of development, leading to large number of models that need coordination, collaboration, and discipline management. Model Management (MoM) is a possible approach to manage inter-related collections of models among which Model Federation (MF) provides unique capabilities, like independence of development in individual modelling domains. There is currently a lack of studies about commonalities, variabilities, and gaps in MF approaches. In this paper, we propose a survey and a critical discussion of carefully selected papers about MF. From 59 contributions collected by experts in MoM, we selected, and classified, 23 papers. We extract the main trends we observed, according to our Classification. We then critically review the Classification, and discuss important gaps found in our corpus. The survey results and artefacts are all available online.
Hallak, Yara; Blouin, Dominique; Pautet, Laurent; Saab, Layale; Laborie, Baptiste; Mittal, Rakshit
Model Management at the Renault Virtual Simulation Team: State of Practice, Challenges, and Research Directions Workshop
1st Workshop on Model Management (MoM), Proceedings of 27th International Conference on Model-Driven Engineering Languages and Systems (MODELS '24) : Companion Proceedings, Association for Computing Machinery Linz, Austria, 2024.
Abstract | BibTeX | Altmetric | Dimensions | PlumX | Links:
@workshop{nokey,
title = {Model Management at the Renault Virtual Simulation Team: State of Practice, Challenges, and Research Directions},
author = {Yara Hallak and Dominique Blouin and Laurent Pautet and Layale Saab and Baptiste Laborie and Rakshit Mittal},
doi = {10.1145/3652620.3688223},
year = {2024},
date = {2024-08-13},
urldate = {2024-08-13},
booktitle = {1st Workshop on Model Management (MoM), Proceedings of 27th International Conference on Model-Driven Engineering Languages and Systems (MODELS '24) : Companion Proceedings},
address = {Linz, Austria},
organization = {Association for Computing Machinery},
abstract = {In the automotive industry, new systems are being developed to enhance vehicle safety and driver convenience. These systems are increasingly complex to build and maintain. To develop these systems Renault makes intensive use of simulation and must deal with thousands of models. This huge number of models must be well managed. %For instance their validity must be well specified to ensure that the employed models correctly represent the simulated systems. To manage these models, Renault has developed the SysML-based Model Identity Card (MIC), used with a Model-Based Simulation (MBSi) approach. However, despite this first solution, managing simulation models remains a difficult task. In this paper, we describe the current simulation model management approaches used at Renault, and their shortcomings and challenges in the modelling and simulation of complex automotive systems. We use Advanced Driver Assistance System (ADAS) and its Automatic Emergency Breaking (AEB) sub-system as examples to illustrate the utilization of the MIC and demonstrate current practices. From these examples, we derive main challenges faced by the virtual simulation team and propose research directions to solve them, based on state of the art methodologies for simulation models' validation and verification management.},
keywords = {},
pubstate = {published},
tppubtype = {workshop}
}
In the automotive industry, new systems are being developed to enhance vehicle safety and driver convenience. These systems are increasingly complex to build and maintain. To develop these systems Renault makes intensive use of simulation and must deal with thousands of models. This huge number of models must be well managed. %For instance their validity must be well specified to ensure that the employed models correctly represent the simulated systems. To manage these models, Renault has developed the SysML-based Model Identity Card (MIC), used with a Model-Based Simulation (MBSi) approach. However, despite this first solution, managing simulation models remains a difficult task. In this paper, we describe the current simulation model management approaches used at Renault, and their shortcomings and challenges in the modelling and simulation of complex automotive systems. We use Advanced Driver Assistance System (ADAS) and its Automatic Emergency Breaking (AEB) sub-system as examples to illustrate the utilization of the MIC and demonstrate current practices. From these examples, we derive main challenges faced by the virtual simulation team and propose research directions to solve them, based on state of the art methodologies for simulation models' validation and verification management.
Mittal, Rakshit; Parveen, Rizwan; Vangheluwe, Hans
Modeling a Cruise-Control System Using OpenModelica and Verifying Safety Requirements Using UPPAAL (hands-on) Miscellaneous
Proceedings of the 5th Summer School on Cyber-Physical Systems and Internet-of-Things (SS-CPSIoT), 2024.
Abstract | BibTeX | Altmetric | Dimensions | PlumX | Links:
@misc{24-cpsiot,
title = {Modeling a Cruise-Control System Using OpenModelica and Verifying Safety Requirements Using UPPAAL (hands-on)},
author = {Rakshit Mittal and Rizwan Parveen and Hans Vangheluwe},
editor = {Lech Jóźwiak},
url = {https://about.rakshitmittal.net/wp-content/uploads/2024/07/presentations-24-cpsiot.pdf},
doi = {10.5281/zenodo.12607601},
year = {2024},
date = {2024-07-01},
urldate = {2024-07-01},
volume = {5},
publisher = {MECONet},
address = {Budva, Montenegro},
abstract = {This tutorial is the first in a series of 2 tutorials about the modeling, verification, analysis, and deployment of cyber-physical systems using multiple formalisms. In the first 90 minutes, students will model the physics of a vehicular cruise-control system using the Open-Sourced software called OpenModelica. Students will use concepts of Ordinary Differential Equations to implement the vehicle using the object-oriented, physics-based formalism called Modelica. They will also implement a PID controller and using optimization techniques, find the best parameters for the PID controller by simulating the controller, plant, and environment together. In the second 90 minutes, students will verify the safety of the controller that they have designed by modelling the system as a timed-automata. They will use the Open-Sourced software called UPPAAL to model the requirement and the system. Then they will use the inbuilt model-checker in UPPAAL to verify that the requirements are met, to provide a formal guarantee of the safety of their system. In this first tutorial students will learn important engineering concepts of system modelling theory, causal and acausal block diagrams modeling and simulation, timed automata modeling and simulation, requirements specification, and formal verification of systems.},
howpublished = {Proceedings of the 5th Summer School on Cyber-Physical Systems and Internet-of-Things (SS-CPSIoT)},
keywords = {},
pubstate = {published},
tppubtype = {misc}
}
This tutorial is the first in a series of 2 tutorials about the modeling, verification, analysis, and deployment of cyber-physical systems using multiple formalisms. In the first 90 minutes, students will model the physics of a vehicular cruise-control system using the Open-Sourced software called OpenModelica. Students will use concepts of Ordinary Differential Equations to implement the vehicle using the object-oriented, physics-based formalism called Modelica. They will also implement a PID controller and using optimization techniques, find the best parameters for the PID controller by simulating the controller, plant, and environment together. In the second 90 minutes, students will verify the safety of the controller that they have designed by modelling the system as a timed-automata. They will use the Open-Sourced software called UPPAAL to model the requirement and the system. Then they will use the inbuilt model-checker in UPPAAL to verify that the requirements are met, to provide a formal guarantee of the safety of their system. In this first tutorial students will learn important engineering concepts of system modelling theory, causal and acausal block diagrams modeling and simulation, timed automata modeling and simulation, requirements specification, and formal verification of systems.
Tran, Hai Nam; Singhoff, Frank; Hugues, Jerome; Dissaux, Pierre; Lewis, Bruce; Mittal, Rakshit; Blouin, Dominique; Bhobe, Anish; Pautet, Laurent; Bae, Kyungmin; Olveckzy, Peter Csaba; Larson, Brian; Ahmad, Ehsan; Kosmidis, Leonidas; Valente, Hugo; de Miguel, Miguel A; Pérez, Ángel G; Alejandro Alonso,; Zamorano, Juan; de la Puente, Juan A
ADEPT 2023 Workshop Summary Proceedings Article
In: Ada User Journal, pp. 28 – 30, Ada Europe 2024.
@inproceedings{nokey,
title = {ADEPT 2023 Workshop Summary},
author = {Hai Nam Tran and Frank Singhoff and Jerome Hugues and Pierre Dissaux and Bruce Lewis and Rakshit Mittal and Dominique Blouin and Anish Bhobe and Laurent Pautet and Kyungmin Bae and Peter Csaba Olveckzy and Brian Larson and Ehsan Ahmad and Leonidas Kosmidis and Hugo Valente and Miguel A de Miguel and Ángel G Pérez and Alejandro Alonso, and Juan Zamorano and Juan A de la Puente},
url = {https://www.ada-europe.org/archive/auj/auj-45-1-withcovers.pdf},
year = {2024},
date = {2024-03-01},
urldate = {2024-03-01},
booktitle = {Ada User Journal},
journal = {Ada User Journal},
volume = {45},
number = {1},
pages = {28 - 30},
organization = {Ada Europe},
abstract = {The Architecture Analysis and Design Language (AADL) is a SAE standard for modeling both hardware and software architecture of embedded systems. Widely embraced by stakeholders in critical real-time embedded systems, the AADL standard is used to address a large set of concerns including performances (latency, schedulability), safety, and security. The ADEPT workshop aims to present and report on current projects in the field of design, implementation, and verification of critical real-time embedded systems where AADL is a first-citizen technology. This article is a summary of the second edition of the workshop in 2023.},
keywords = {},
pubstate = {published},
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The Architecture Analysis and Design Language (AADL) is a SAE standard for modeling both hardware and software architecture of embedded systems. Widely embraced by stakeholders in critical real-time embedded systems, the AADL standard is used to address a large set of concerns including performances (latency, schedulability), safety, and security. The ADEPT workshop aims to present and report on current projects in the field of design, implementation, and verification of critical real-time embedded systems where AADL is a first-citizen technology. This article is a summary of the second edition of the workshop in 2023.
Mittal, Rakshit; Blouin, Dominique
Facilitating AADL model processing and analysis with OSATE-DIM Workshop
2nd ADEPT workshop: AADL by its practitioners, 27th Ada Europe International Conference (AEiC), vol. 45, no. 1, Ada Europe Lisbon, Portugal, 2024.
@workshop{nokey,
title = {Facilitating AADL model processing and analysis with OSATE-DIM},
author = {Rakshit Mittal and Dominique Blouin},
url = {https://www.ada-europe.org/archive/auj/auj-45-1-withcovers.pdf},
year = {2024},
date = {2024-03-01},
urldate = {2024-03-01},
booktitle = {2nd ADEPT workshop: AADL by its practitioners, 27th Ada Europe International Conference (AEiC)},
journal = {Ada User Journal},
volume = {45},
number = {1},
pages = {55 - 58},
address = {Lisbon, Portugal},
organization = {Ada Europe},
abstract = {The Architecture Analysis and Design Language (AADL) is a rich component-based language for modelling embedded systems. To ease processing AADL models, OSATE, the reference tool for AADL, provides the ‘instance’ model derived from base ‘declarative’ model/s. An instance model represents the operational view of a declarative model in a simple object tree where information is flattened (with no component extensions / refinements) so that tools can easily analyze the model. Note that information is lost in instantiation. Since the instance model is a (un-symmetric) ‘view’ of the declarative model, the capability to directly modify the instance model requires a solution to the view-update problem. We demonstrate the OSATE Declarative-Instance Mapping Tool (OSATE-DIM) to perform incremental deinstantiation in AADL. OSATE-DIM significantly eases the development of AADL model processing tools for analysis and code generation.},
keywords = {},
pubstate = {published},
tppubtype = {workshop}
}
The Architecture Analysis and Design Language (AADL) is a rich component-based language for modelling embedded systems. To ease processing AADL models, OSATE, the reference tool for AADL, provides the ‘instance’ model derived from base ‘declarative’ model/s. An instance model represents the operational view of a declarative model in a simple object tree where information is flattened (with no component extensions / refinements) so that tools can easily analyze the model. Note that information is lost in instantiation. Since the instance model is a (un-symmetric) ‘view’ of the declarative model, the capability to directly modify the instance model requires a solution to the view-update problem. We demonstrate the OSATE Declarative-Instance Mapping Tool (OSATE-DIM) to perform incremental deinstantiation in AADL. OSATE-DIM significantly eases the development of AADL model processing tools for analysis and code generation.
Deantoni, Julien; Muñoz, Paula; Gomes, Cláudio; Verbrugge, Clark; Mittal, Rakshit; Heinrich, Robert; Bellis, Stijn; Vallecillo, Antonio
Quantifying and combining uncertainty for improving the behavior of Digital Twin Systems Journal Article
In: at – Automatisierungstechnik, vol. 73, 2024.
@article{2024-deantoni-arxiv-j,
title = {Quantifying and combining uncertainty for improving the behavior of Digital Twin Systems},
author = {Julien Deantoni and Paula Muñoz and Cláudio Gomes and Clark Verbrugge and Rakshit Mittal and Robert Heinrich and Stijn Bellis and Antonio Vallecillo},
url = {https://arxiv.org/abs/2402.10535
https://doi.org/10.48550/ARXIV.2402.10535},
year = {2024},
date = {2024-01-01},
urldate = {2024-01-01},
journal = {at - Automatisierungstechnik},
volume = {73},
organization = {De Gruyter},
abstract = {Uncertainty is an inherent property of any complex system, especially those that integrate physical parts or operate in real environments. In this paper, we focus on the Digital Twins of adaptive systems, which are particularly complex to design, verify, and optimize. One of the problems of having two systems (the physical one and its digital replica) is that their behavior may not always be consistent. In addition, both twins are normally subject to different types of uncertainties, which complicates their comparison. In this paper we propose the explicit representation and treatment of the uncertainty of both twins, and show how this enables a more accurate comparison of their behaviors. Furthermore, this allows us to reduce the overall system uncertainty and improve its behavior by properly averaging the individual uncertainties of the two twins. An exemplary incubator system is used to illustrate and validate our proposal. },
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Uncertainty is an inherent property of any complex system, especially those that integrate physical parts or operate in real environments. In this paper, we focus on the Digital Twins of adaptive systems, which are particularly complex to design, verify, and optimize. One of the problems of having two systems (the physical one and its digital replica) is that their behavior may not always be consistent. In addition, both twins are normally subject to different types of uncertainties, which complicates their comparison. In this paper we propose the explicit representation and treatment of the uncertainty of both twins, and show how this enables a more accurate comparison of their behaviors. Furthermore, this allows us to reduce the overall system uncertainty and improve its behavior by properly averaging the individual uncertainties of the two twins. An exemplary incubator system is used to illustrate and validate our proposal.
2023
Mittal, Rakshit; Eslampanah, Raheleh; Lima, Lucas; Vangheluwe, Hans; Blouin, Dominique
Towards an Ontological Framework for Validity Frames Workshop
20th Workshop on Model Driven Engineering, Verification and Validation (MoDeVVa), 26th ACM/IEEE International Conference on Model Driven Engineering Languages and Systems Companion (MODELS-C), Institute of Electrical and Electronics Engineers, Vasteras, Sweden, 2023.
Abstract | BibTeX | Altmetric | Dimensions | PlumX | Links:
@workshop{10350613,
title = {Towards an Ontological Framework for Validity Frames},
author = {Rakshit Mittal and Raheleh Eslampanah and Lucas Lima and Hans Vangheluwe and Dominique Blouin},
doi = {10.1109/MODELS-C59198.2023.00128},
year = {2023},
date = {2023-10-01},
urldate = {2023-10-01},
booktitle = {20th Workshop on Model Driven Engineering, Verification and Validation (MoDeVVa), 26th ACM/IEEE International Conference on Model Driven Engineering Languages and Systems Companion (MODELS-C)},
pages = {801-805},
publisher = {Institute of Electrical and Electronics Engineers},
address = {Vasteras, Sweden},
abstract = {A Validity Frame captures the set of contexts in which a model (and its analysis, often by means of simulation) of a system is able to replace that system with respect to questions about a set of salient properties of interest. Even though the utility of validity frames has been reported in current literature, there does not exist any precise and general definition of the concept. This paper presents our on-going development of a framework for designing and using validity frames. This framework both uses and supports model management. We have developed an ontology in order to precisely define the concepts of the model validity domain. The framework currently consists of ontological definitions integrated in a workflow model that describes a general experiment, validation experiments, and the construction of validity frames. A simple resistor model validation case-study is used as running example to describe the concepts. The validity frames of different resistor models are computed. How to use the framework in different scenarios is sketched.},
keywords = {},
pubstate = {published},
tppubtype = {workshop}
}
A Validity Frame captures the set of contexts in which a model (and its analysis, often by means of simulation) of a system is able to replace that system with respect to questions about a set of salient properties of interest. Even though the utility of validity frames has been reported in current literature, there does not exist any precise and general definition of the concept. This paper presents our on-going development of a framework for designing and using validity frames. This framework both uses and supports model management. We have developed an ontology in order to precisely define the concepts of the model validity domain. The framework currently consists of ontological definitions integrated in a workflow model that describes a general experiment, validation experiments, and the construction of validity frames. A simple resistor model validation case-study is used as running example to describe the concepts. The validity frames of different resistor models are computed. How to use the framework in different scenarios is sketched.
Blouin, Dominique; Bhobe, Anish; Mittal, Rakshit; Borde, Etienne
Embedded Systems Modeling, Analysis and Automatic Code Generation with AADL and RAMSES (hands-on) Miscellaneous
Proceedings of the 4th Summer School on Cyber-Physical Systems and Internet-of-Things (SS-CPSIoT), 2023.
BibTeX | Altmetric | Dimensions | PlumX | Links:
@misc{cpsiot-23,
title = {Embedded Systems Modeling, Analysis and Automatic Code Generation with AADL and RAMSES (hands-on)},
author = {Dominique Blouin and Anish Bhobe and Rakshit Mittal and Etienne Borde},
editor = {Lech Jóźwiak and Radovan Stojanovic and Christos Antonopoulos
},
url = {https://zenodo.org/records/8113313},
doi = {10.5281/zenodo.8113312},
year = {2023},
date = {2023-07-04},
urldate = {2023-07-04},
volume = {4},
pages = {316-367},
publisher = {MECONet},
address = {Budva, Montenegro},
howpublished = {Proceedings of the 4th Summer School on Cyber-Physical Systems and Internet-of-Things (SS-CPSIoT)},
keywords = {},
pubstate = {published},
tppubtype = {misc}
}
2022
Jain, Vaibhav; Selvaraj, Abirami; Mittal, Rakshit; Rani, Priya; Ramaniharan, Anandh; Fredo, Jack
Automated Diagnosis of Autism Spectrum Disorder Condition Using Shape Based Features Extracted from Brainstem Conference
Challenges of Trustable AI and Added-Value on Health, vol. 294, Medical Informatics Europe (MIE) Conference European Federation for Medical Informatics IOS Press, Nice, France, 2022, ISBN: 9781643682846.
Abstract | BibTeX | Altmetric | Dimensions | PlumX | Links:
@conference{mie2022,
title = {Automated Diagnosis of Autism Spectrum Disorder Condition Using Shape Based Features Extracted from Brainstem},
author = {Vaibhav Jain and Abirami Selvaraj and Rakshit Mittal and Priya Rani and Anandh Ramaniharan and Jack Fredo},
doi = {10.3233/SHTI220395},
isbn = {9781643682846},
year = {2022},
date = {2022-05-26},
urldate = {2022-01-01},
booktitle = {Challenges of Trustable AI and Added-Value on Health},
journal = {Studies in health technology and informatics},
volume = {294},
publisher = {IOS Press},
address = {Nice, France},
organization = {European Federation for Medical Informatics},
series = {Medical Informatics Europe (MIE) Conference},
abstract = {Alterations to the brainstem can hamper cognitive functioning, including audiovisual and behavioral disintegration, leading to individuals with Autism Spectrum Disorder (ASD) face challenges in social interaction. In this study, a process pipeline for the diagnosis of ASD has been proposed, based on geometrical and Zernike moments features, extracted from the brainstem of ASD subjects. The subjects considered for this study are obtained from publicly available data base ABIDE (300 ASD and 300 typically developing (TD)). Distance regularized level set (DRLSE) method has been used to segment the brainstem region from the midsagittal view of MRI data. Similarity measures were used to validate the segmented images against the ground truth images. Geometrical and Zernike moments features were extracted from the segmented images. The significant features were used to train Support vector machine (SVM) classifier to perform classification between ASD and TD subjects. The similarity results show high matching between DRLSE segmented brainstem and ground truth with high similarity index scores of Pearson Heron-II (PH II)= 0.9740 and Sokal and Sneath-II (SS II)= 0.9727. The SVM classifier achieved 70.53% accuracy to classify ASD and TD subjects. Thus, the process pipeline proposed in this study is able to achieve good accuracy in the classification of ASD subjects.},
keywords = {},
pubstate = {published},
tppubtype = {conference}
}
Alterations to the brainstem can hamper cognitive functioning, including audiovisual and behavioral disintegration, leading to individuals with Autism Spectrum Disorder (ASD) face challenges in social interaction. In this study, a process pipeline for the diagnosis of ASD has been proposed, based on geometrical and Zernike moments features, extracted from the brainstem of ASD subjects. The subjects considered for this study are obtained from publicly available data base ABIDE (300 ASD and 300 typically developing (TD)). Distance regularized level set (DRLSE) method has been used to segment the brainstem region from the midsagittal view of MRI data. Similarity measures were used to validate the segmented images against the ground truth images. Geometrical and Zernike moments features were extracted from the segmented images. The significant features were used to train Support vector machine (SVM) classifier to perform classification between ASD and TD subjects. The similarity results show high matching between DRLSE segmented brainstem and ground truth with high similarity index scores of Pearson Heron-II (PH II)= 0.9740 and Sokal and Sneath-II (SS II)= 0.9727. The SVM classifier achieved 70.53% accuracy to classify ASD and TD subjects. Thus, the process pipeline proposed in this study is able to achieve good accuracy in the classification of ASD subjects.
Mittal, Rakshit; Prince, A. Amalin; Fredo, Agastinose Ronickom Jac
Time-Sliced Architecture for Efficient Accelerator to Detrend High-Definition Electroencephalograms Journal Article
In: IEEE Transactions on Instrumentation and Measurement, vol. 71, pp. 1-9, 2022, ISSN: 1557-9662.
Abstract | BibTeX | Altmetric | Dimensions | PlumX | Links:
@article{9789133,
title = {Time-Sliced Architecture for Efficient Accelerator to Detrend High-Definition Electroencephalograms},
author = {Rakshit Mittal and A. Amalin Prince and Agastinose Ronickom Jac Fredo},
doi = {10.1109/TIM.2022.3180418},
issn = {1557-9662},
year = {2022},
date = {2022-01-01},
journal = {IEEE Transactions on Instrumentation and Measurement},
volume = {71},
pages = {1-9},
abstract = {Measuring electroencephalography (EEG) signals has a variety of important applications. Most processing systems use statistical machine learning algorithms. To increase accuracy of such systems, more data are measured in the form of increased channel count, called high-definition EEG (HD-EEG). EEG processing is hampered by noise from different instruments. While traditional detrending algorithms are highly resource-intensive, the problem is compounded for HD-EEG detrending. The generic-compounding architecture is not scalable. In such an architecture, one instance of the hardware accelerator is used for each channel. This is unsuitable for wearable devices which have limited computational and energy resources. In this article, we propose a time-sliced architecture to optimize resource and power utilization for a multi-channeled system. This is accomplished using time-division multiplexers and demultiplexers to share resources between different channels. The adaptive maximum–mean–minimum (AMaMeMi) filter is a computationally efficient algorithm, reported earlier for detrending EEGs. We apply guidelines of the proposed architecture, on the AMaMeMi filter, to design an efficient HD-EEG detrending hardware accelerator. The proposed accelerator is implemented for various channel counts. We use the Xilinx field-programmable gate array with part number XC7VX980T-1FFG1930 for implementation. We verify the correctness of the proposed architecture by comparing its output with that of the generic-compounding architecture. For a 1024-channeled system, the proposed time-sliced architecture provides 99% reduction in lookup table utilization, 70% in flip-flop utilization, 95% in area utilization, and 70% in estimated power utilization.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Measuring electroencephalography (EEG) signals has a variety of important applications. Most processing systems use statistical machine learning algorithms. To increase accuracy of such systems, more data are measured in the form of increased channel count, called high-definition EEG (HD-EEG). EEG processing is hampered by noise from different instruments. While traditional detrending algorithms are highly resource-intensive, the problem is compounded for HD-EEG detrending. The generic-compounding architecture is not scalable. In such an architecture, one instance of the hardware accelerator is used for each channel. This is unsuitable for wearable devices which have limited computational and energy resources. In this article, we propose a time-sliced architecture to optimize resource and power utilization for a multi-channeled system. This is accomplished using time-division multiplexers and demultiplexers to share resources between different channels. The adaptive maximum–mean–minimum (AMaMeMi) filter is a computationally efficient algorithm, reported earlier for detrending EEGs. We apply guidelines of the proposed architecture, on the AMaMeMi filter, to design an efficient HD-EEG detrending hardware accelerator. The proposed accelerator is implemented for various channel counts. We use the Xilinx field-programmable gate array with part number XC7VX980T-1FFG1930 for implementation. We verify the correctness of the proposed architecture by comparing its output with that of the generic-compounding architecture. For a 1024-channeled system, the proposed time-sliced architecture provides 99% reduction in lookup table utilization, 70% in flip-flop utilization, 95% in area utilization, and 70% in estimated power utilization.
Mittal, Rakshit; Blouin, Dominique
OSATE-DIM solves the instance model-view update problem in AADL Conference
Proceedings of the 25th International Conference on Model Driven Engineering Languages and Systems: Companion Proceedings, MODELS '22 Association for Computing Machinery, Montreal, Quebec, Canada, 2022, ISBN: 9781450394673.
Abstract | BibTeX | Altmetric | Dimensions | PlumX | Links:
@conference{10.1145/3550356.3559083,
title = {OSATE-DIM solves the instance model-view update problem in AADL},
author = {Rakshit Mittal and Dominique Blouin},
url = {https://doi.org/10.1145/3550356.3559083},
doi = {10.1145/3550356.3559083},
isbn = {9781450394673},
year = {2022},
date = {2022-01-01},
urldate = {2022-01-01},
booktitle = {Proceedings of the 25th International Conference on Model Driven Engineering Languages and Systems: Companion Proceedings},
pages = {1–6},
publisher = {Association for Computing Machinery},
address = {Montreal, Quebec, Canada},
series = {MODELS '22},
abstract = {AADL (Architecture Analysis and Design Language) is a rich modeling language for embedded systems through several constructs such as component extension and refinement to promote modularity of declarative specifications. To ease the processing of AADL models by tools, OSATE, the reference tool for AADL, defines another model computed from declarative models which results in a single tree system where all information is readily available. Tools can efficiently use this readily available information to analyze the system. An automated backward transformation (deinstantiation) from instance models to declarative models is missing to update the corresponding declarative specification given changes that have been performed on the instance model. Since the instance model is a 'view' of the declarative model, this is a view-update problem. We demonstrate the OSATE Declarative-Instance Mapping Tool (OSATE-DIM), to perform incremental deinstantiation in AADL. This tool significantly eases the development of AADL analysis and code generation tools.},
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AADL (Architecture Analysis and Design Language) is a rich modeling language for embedded systems through several constructs such as component extension and refinement to promote modularity of declarative specifications. To ease the processing of AADL models by tools, OSATE, the reference tool for AADL, defines another model computed from declarative models which results in a single tree system where all information is readily available. Tools can efficiently use this readily available information to analyze the system. An automated backward transformation (deinstantiation) from instance models to declarative models is missing to update the corresponding declarative specification given changes that have been performed on the instance model. Since the instance model is a 'view' of the declarative model, this is a view-update problem. We demonstrate the OSATE Declarative-Instance Mapping Tool (OSATE-DIM), to perform incremental deinstantiation in AADL. This tool significantly eases the development of AADL analysis and code generation tools.
Bhattacharya, Pritam; Joshi, Swaroop; Bandyopadhyay, Soumyadip; Mittal, Rakshit
Virtual Computer Science Education in India: Challenges and Opportunities Conference
Proceedings of the International Conference on Best Innovative Teaching Strategies (ICON-BITS 2021), SSRN, Goa, India, 2022.
Abstract | BibTeX | Altmetric | Dimensions | PlumX | Links:
@conference{PPR:PPR604590,
title = {Virtual Computer Science Education in India: Challenges and Opportunities},
author = {Pritam Bhattacharya and Swaroop Joshi and Soumyadip Bandyopadhyay and Rakshit Mittal},
url = {https://papers.ssrn.com/sol3/papers.cfm?abstract_id=4026251},
doi = {10.2139/ssrn.4026251},
year = {2022},
date = {2022-01-01},
urldate = {2022-01-01},
booktitle = {Proceedings of the International Conference on Best Innovative Teaching Strategies (ICON-BITS 2021)},
pages = {264 - 267},
publisher = {SSRN},
address = {Goa, India},
abstract = {In the wake of the COVID-19 pandemic, institutes for higher education worldwide, including in India, were forced to migrate to fully online classes. A country like India, with limited internet connectivity and infrastructure as well as its socio-economic, presents unique challenges. In this article, we discuss how education in India, particularly in the field of Computer Science (CS), is affected, and where the challenges lie for students, faculty, researchers, and administrators. We share our experiences related to the migration of CS classes online in a reputed engineering institute in India with more than 15,000 students over three campuses. We also discuss ways to overcome the challenges posed by the digital divide. The main objective of this article is to generate interesting discussions that could potentially lead to advancements in information and communication technologies geared particularly towards CS education in developing countries.},
keywords = {},
pubstate = {published},
tppubtype = {conference}
}
In the wake of the COVID-19 pandemic, institutes for higher education worldwide, including in India, were forced to migrate to fully online classes. A country like India, with limited internet connectivity and infrastructure as well as its socio-economic, presents unique challenges. In this article, we discuss how education in India, particularly in the field of Computer Science (CS), is affected, and where the challenges lie for students, faculty, researchers, and administrators. We share our experiences related to the migration of CS classes online in a reputed engineering institute in India with more than 15,000 students over three campuses. We also discuss ways to overcome the challenges posed by the digital divide. The main objective of this article is to generate interesting discussions that could potentially lead to advancements in information and communication technologies geared particularly towards CS education in developing countries.
Mittal, Rakshit; Blouin, Dominique; Bhobe, Anish; Bandyopadhyay, Soumyadip
Solving the instance model-view update problem in AADL Conference
Proceedings of the 25th International Conference on Model Driven Engineering Languages and Systems, MODELS '22 Association for Computing Machinery, Montreal, Quebec, Canada, 2022, ISBN: 9781450394666.
Abstract | BibTeX | Altmetric | Dimensions | PlumX | Links:
@conference{10.1145/3550355.3552396,
title = {Solving the instance model-view update problem in AADL},
author = {Rakshit Mittal and Dominique Blouin and Anish Bhobe and Soumyadip Bandyopadhyay},
url = {https://doi.org/10.1145/3550355.3552396},
doi = {10.1145/3550355.3552396},
isbn = {9781450394666},
year = {2022},
date = {2022-01-01},
urldate = {2022-01-01},
booktitle = {Proceedings of the 25th International Conference on Model Driven Engineering Languages and Systems},
pages = {55–65},
publisher = {Association for Computing Machinery},
address = {Montreal, Quebec, Canada},
series = {MODELS '22},
abstract = {The Architecture Analysis and Design Language (AADL) is a rich language for modeling embedded systems through several constructs such as component extension and refinement to promote modularity of component declarations. To ease processing AADL models, OSATE, the reference tool for AADL, defines another model (namely 'instance' model) computed from a base 'declarative' model/s. An instance model is a simple object tree where all information from the declarative model is flattened so that tools can easily use this information to analyze the system. However for modifications, they have to make changes in the complex declarative model since there is no automated backward transformation (deinstantiation) from instance to declarative models. Since the instance model is a 'view' of the declarative model, this is a view-update problem. In this paper, we propose the OSATE Declarative-Instance Mapping Tool (OSATE-DIM1), an Eclipse plugin for deinstantiation of AADL models implementing a solution of this view-update problem. We evaluate OSATE-DIM with a benchmark of existing AADL model processing tools and verify the correctness of our deinstantiation transformations. We also discuss how our approach could be useful for decompilation of Object-Oriented languages' intermediate representations.},
keywords = {},
pubstate = {published},
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}
The Architecture Analysis and Design Language (AADL) is a rich language for modeling embedded systems through several constructs such as component extension and refinement to promote modularity of component declarations. To ease processing AADL models, OSATE, the reference tool for AADL, defines another model (namely 'instance' model) computed from a base 'declarative' model/s. An instance model is a simple object tree where all information from the declarative model is flattened so that tools can easily use this information to analyze the system. However for modifications, they have to make changes in the complex declarative model since there is no automated backward transformation (deinstantiation) from instance to declarative models. Since the instance model is a 'view' of the declarative model, this is a view-update problem. In this paper, we propose the OSATE Declarative-Instance Mapping Tool (OSATE-DIM1), an Eclipse plugin for deinstantiation of AADL models implementing a solution of this view-update problem. We evaluate OSATE-DIM with a benchmark of existing AADL model processing tools and verify the correctness of our deinstantiation transformations. We also discuss how our approach could be useful for decompilation of Object-Oriented languages' intermediate representations.
Mittal, Rakshit; Prince, A. Amalin
Catalogic Systematic Literature Review of Hardware-Accelerated Neurodiagnostic Systems Book Chapter
In: Murugappan, M.; Rajamanickam, Yuvaraj (Ed.): Biomedical Signals Based Computer-Aided Diagnosis for Neurological Disorders, pp. 187–232, Springer International Publishing, Cham, 2022, ISBN: 978-3-030-97845-7.
Abstract | BibTeX | Altmetric | Dimensions | PlumX | Links:
@inbook{Mittal2022,
title = {Catalogic Systematic Literature Review of Hardware-Accelerated Neurodiagnostic Systems},
author = {Rakshit Mittal and A. Amalin Prince},
editor = {M. Murugappan and Yuvaraj Rajamanickam},
url = {https://doi.org/10.1007/978-3-030-97845-7_10},
doi = {10.1007/978-3-030-97845-7_10},
isbn = {978-3-030-97845-7},
year = {2022},
date = {2022-01-01},
booktitle = {Biomedical Signals Based Computer-Aided Diagnosis for Neurological Disorders},
pages = {187–232},
publisher = {Springer International Publishing},
address = {Cham},
abstract = {Computer-aided diagnosis (CAD) plays a key role in automating and enhancing the diagnosis of complex neurological disorders. Computers are not just used to automate the final diagnosis step but for the design of sensors, the preprocessing unit, and the processing unit as well. Today, it is an essential requirement that these CAD systems have low latency and low power consumption, which is not possible using a traditional software-based system that utilizes a complex processor to execute an operating system that supports the diagnostic application. The processor is clocked at a high frequency to execute all such supplementary processes, which increases the power consumption of a software-based system. Moreover, software-based systems inherently have high latency. Hardware accelerators overcome these limitations. Hardware acceleration is supported by the advent of the field-programmable gate array (FPGA), allowing rapid testing and deployment of hardware systems. Moreover, the novel neuromorphic platform has the potential to efficiently accelerate neural networks as well, which was not possible with the FPGA.},
keywords = {},
pubstate = {published},
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Computer-aided diagnosis (CAD) plays a key role in automating and enhancing the diagnosis of complex neurological disorders. Computers are not just used to automate the final diagnosis step but for the design of sensors, the preprocessing unit, and the processing unit as well. Today, it is an essential requirement that these CAD systems have low latency and low power consumption, which is not possible using a traditional software-based system that utilizes a complex processor to execute an operating system that supports the diagnostic application. The processor is clocked at a high frequency to execute all such supplementary processes, which increases the power consumption of a software-based system. Moreover, software-based systems inherently have high latency. Hardware accelerators overcome these limitations. Hardware acceleration is supported by the advent of the field-programmable gate array (FPGA), allowing rapid testing and deployment of hardware systems. Moreover, the novel neuromorphic platform has the potential to efficiently accelerate neural networks as well, which was not possible with the FPGA.
2021
Mittal, Rakshit; Blouin, Dominique; Bandyopadhyay, Soumyadip
PNPEq: Verification of Scheduled Conditional Behavior in Embedded Software using Petri Nets Conference
2021 28th Asia-Pacific Software Engineering Conference (APSEC), IEEE, Taipei, Taiwan, 2021, ISSN: 2640-0715.
Abstract | BibTeX | Altmetric | Dimensions | PlumX | Links:
@conference{Mittal2021,
title = {PNPEq: Verification of Scheduled Conditional Behavior in Embedded Software using Petri Nets},
author = {Rakshit Mittal and Dominique Blouin and Soumyadip Bandyopadhyay},
url = {https://ieeexplore.ieee.org/document/9712023},
doi = {10.1109/APSEC53868.2021.00059},
issn = {2640-0715},
year = {2021},
date = {2021-12-01},
urldate = {2021-12-01},
booktitle = {2021 28th Asia-Pacific Software Engineering Conference (APSEC)},
pages = {509-514},
publisher = {IEEE},
address = {Taipei, Taiwan},
abstract = {Software for embedded systems goes through a scheduling phase where it is subjected to optimizing transformations. In such a scenario, validating the preservation of semantics across the transformation is essential. In this paper, we present PNPEq (Petri Net Program Equivalence), an ongoing work on a novel translation validation technique to handle various schedule-time conditional optimizations among others. The method makes use of a reduced size Petri net model integrating SMT solvers for validating arithmetic transformations. The approach is illustrated with a simple program and its translation, and further validated with a preliminary example suite.},
keywords = {},
pubstate = {published},
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Software for embedded systems goes through a scheduling phase where it is subjected to optimizing transformations. In such a scenario, validating the preservation of semantics across the transformation is essential. In this paper, we present PNPEq (Petri Net Program Equivalence), an ongoing work on a novel translation validation technique to handle various schedule-time conditional optimizations among others. The method makes use of a reduced size Petri net model integrating SMT solvers for validating arithmetic transformations. The approach is illustrated with a simple program and its translation, and further validated with a preliminary example suite.
Tekinerdogan, Bedir; Mittal, Rakshit; Al-Ali, Rima; Iacono, Mauro; Navarro-López, Eva; Bandyopadhyay, Soumyadip; Vanherpen, Ken; Barišić, Ankica; Taveter, Kuldar
A feature-based ontology for cyber-physical systems Book Chapter
In: Tekinerdogan, Bedir; Blouin, Dominique; Vangheluwe, Hans; Goulão, Miguel; Carreira, Paulo; Amaral, Vasco (Ed.): Multi-Paradigm Modelling Approaches for Cyber-Physical Systems, Chapter 3, pp. 45-65, Academic Press, 2021, ISBN: 978-0-12-819105-7.
Abstract | BibTeX | Altmetric | Dimensions | PlumX | Links:
@inbook{Tekinerdogan2021,
title = {A feature-based ontology for cyber-physical systems},
author = {Bedir Tekinerdogan and Rakshit Mittal and Rima Al-Ali and Mauro Iacono and Eva Navarro-López and Soumyadip Bandyopadhyay and Ken Vanherpen and Ankica Barišić and Kuldar Taveter},
editor = {Bedir Tekinerdogan and Dominique Blouin and Hans Vangheluwe and Miguel Goulão and Paulo Carreira and Vasco Amaral},
url = {https://www.sciencedirect.com/science/article/pii/B9780128191057000088},
doi = {10.1016/B978-0-12-819105-7.00008-8},
isbn = {978-0-12-819105-7},
year = {2021},
date = {2021-01-01},
urldate = {2021-01-01},
booktitle = {Multi-Paradigm Modelling Approaches for Cyber-Physical Systems},
pages = {45-65},
publisher = {Academic Press},
chapter = {3},
abstract = {In this chapter a feature-based ontology of cyber-physical systems is provided. We have adopted feature modelling to represent the common and variant features of a CPS. The CPS feature model has been developed after a thorough domain analysis on CPS. The resulting feature model shows the configuration space for developing CPSs. Two different case studies on CPS have been used to illustrate how to derive a concrete CPS configuration.},
keywords = {},
pubstate = {published},
tppubtype = {inbook}
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In this chapter a feature-based ontology of cyber-physical systems is provided. We have adopted feature modelling to represent the common and variant features of a CPS. The CPS feature model has been developed after a thorough domain analysis on CPS. The resulting feature model shows the configuration space for developing CPSs. Two different case studies on CPS have been used to illustrate how to derive a concrete CPS configuration.
Mittal, Rakshit; Prince, A. Amalin; Nalband, Saif; Robert, Femi; Fredo, Agastinose Ronickom Jac
Low-Power Hardware Accelerator for Detrending Measured Biopotential Data Journal Article
In: IEEE Transactions on Instrumentation and Measurement, vol. 70, pp. 1-9, 2021, ISSN: 1557-9662.
Abstract | BibTeX | Altmetric | Dimensions | PlumX | Links:
@article{9171901,
title = {Low-Power Hardware Accelerator for Detrending Measured Biopotential Data},
author = {Rakshit Mittal and A. Amalin Prince and Saif Nalband and Femi Robert and Agastinose Ronickom Jac Fredo},
doi = {10.1109/TIM.2020.3018235},
issn = {1557-9662},
year = {2021},
date = {2021-01-01},
journal = {IEEE Transactions on Instrumentation and Measurement},
volume = {70},
pages = {1-9},
abstract = {Biopotential data measurement plays an important role in monitoring the body’s physiological functions. It is affected by noise from various sources for different signals adversely affecting the ability to interpret them. The traditional methods of data detrending are either computationally inefficient, power-intensive, or have high latency. The maximum–mean–minimum (MaMeMi) filter reported for electrocardiogram (ECG) denoising is a computationally efficient algorithm. The MaMeMi filter response depends on two filter coefficients. In the real time, it is difficult to gauge the characteristics of the detected signal beforehand. In this article, we propose an adaptive-MaMeMi (AMaMeMi) filter, which adaptively computes the filter coefficients according to the properties of the input. We have used hardware–software codesign techniques for the optimized implementation of the AMaMeMi filter. The proposed hardware accelerator architecture for the AMaMeMi filter can be used in both adaptive and manual modes of operation. The hardware accelerator is tested for various biopotential signal detrendings, and the single hardware is capable of eliminating baseline wander from all considered measurements with less computational costs and low latency. We implemented the AMaMeMi filter on Xilinx Zynq-7000 system-on-chip (part number XCZ7020-CLG484-1) and statistically verified the results. The hardware accelerator implementation results provide a good correlation with MATLAB simulation results. The hardware accelerator implementation provides an average correlation of 0.9999, a normalized root-mean-square error of 0.0038, and a maximum signal-to-noise ratio (SNR) gain of 19 dB. The low computational complexity of the proposed architecture implies low-power consumption. It consumes 12 mW at 100-MHz clock and 0.7 mW at 500-Hz clock.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Biopotential data measurement plays an important role in monitoring the body’s physiological functions. It is affected by noise from various sources for different signals adversely affecting the ability to interpret them. The traditional methods of data detrending are either computationally inefficient, power-intensive, or have high latency. The maximum–mean–minimum (MaMeMi) filter reported for electrocardiogram (ECG) denoising is a computationally efficient algorithm. The MaMeMi filter response depends on two filter coefficients. In the real time, it is difficult to gauge the characteristics of the detected signal beforehand. In this article, we propose an adaptive-MaMeMi (AMaMeMi) filter, which adaptively computes the filter coefficients according to the properties of the input. We have used hardware–software codesign techniques for the optimized implementation of the AMaMeMi filter. The proposed hardware accelerator architecture for the AMaMeMi filter can be used in both adaptive and manual modes of operation. The hardware accelerator is tested for various biopotential signal detrendings, and the single hardware is capable of eliminating baseline wander from all considered measurements with less computational costs and low latency. We implemented the AMaMeMi filter on Xilinx Zynq-7000 system-on-chip (part number XCZ7020-CLG484-1) and statistically verified the results. The hardware accelerator implementation results provide a good correlation with MATLAB simulation results. The hardware accelerator implementation provides an average correlation of 0.9999, a normalized root-mean-square error of 0.0038, and a maximum signal-to-noise ratio (SNR) gain of 19 dB. The low computational complexity of the proposed architecture implies low-power consumption. It consumes 12 mW at 100-MHz clock and 0.7 mW at 500-Hz clock.
Mittal, Rakshit; Banerjee, Rochishnu; Blouin, Dominique; Bandyopadhyay, Soumyadip
Towards an Approach for Translation Validation of Thread-level Parallelizing Transformations using Colored Petri Nets Best Paper Conference
Proceedings of the 16th International Conference on Software Technologies – ICSOFT, INSTICC SciTePress, 2021, ISSN: 2184-2833.
Abstract | BibTeX | Altmetric | Dimensions | PlumX | Links:
@conference{icsoft21,
title = {Towards an Approach for Translation Validation of Thread-level Parallelizing Transformations using Colored Petri Nets},
author = {Rakshit Mittal and Rochishnu Banerjee and Dominique Blouin and Soumyadip Bandyopadhyay},
doi = {10.5220/0010581005330541},
issn = {2184-2833},
year = {2021},
date = {2021-01-01},
urldate = {2021-01-01},
booktitle = {Proceedings of the 16th International Conference on Software Technologies - ICSOFT},
pages = {533-541},
publisher = {SciTePress},
organization = {INSTICC},
abstract = {Software applications often require the transformation of an input source program into a translated one for optimization. In this process, preserving the semantics across the transformation also called equivalence checking is essential. In this paper, we present ongoing work on a novel translation validation technique for handling loop transformations such as loop swapping and distribution, which cannot be handled by state-of-the-art equivalence checkers. The method makes use of a reduced size Petri net model integrating SMT solvers for validating arithmetic transformations. The approach is illustrated with two simple programs and further validated with a programs benchmark.},
keywords = {},
pubstate = {published},
tppubtype = {conference}
}
Software applications often require the transformation of an input source program into a translated one for optimization. In this process, preserving the semantics across the transformation also called equivalence checking is essential. In this paper, we present ongoing work on a novel translation validation technique for handling loop transformations such as loop swapping and distribution, which cannot be handled by state-of-the-art equivalence checkers. The method makes use of a reduced size Petri net model integrating SMT solvers for validating arithmetic transformations. The approach is illustrated with two simple programs and further validated with a programs benchmark.
Mittal, Rakshit; Prince, A. Amalin; Nalband, Saif; Robert, Femi; Fredo, Agastinose Ronickom Jac
Modified-MaMeMi filter bank for efficient extraction of brainwaves from electroencephalograms Journal Article
In: Biomedical Signal Processing and Control, vol. 69, pp. 102927, 2021, ISSN: 1746-8094.
Abstract | BibTeX | Altmetric | Dimensions | PlumX | Links:
@article{MITTAL2021102927,
title = {Modified-MaMeMi filter bank for efficient extraction of brainwaves from electroencephalograms},
author = {Rakshit Mittal and A. Amalin Prince and Saif Nalband and Femi Robert and Agastinose Ronickom Jac Fredo},
url = {https://www.sciencedirect.com/science/article/pii/S1746809421005243},
doi = {https://doi.org/10.1016/j.bspc.2021.102927},
issn = {1746-8094},
year = {2021},
date = {2021-01-01},
journal = {Biomedical Signal Processing and Control},
volume = {69},
pages = {102927},
abstract = {Electroencephalography (EEG) is an important tool for characterizing the functioning of the brain. Studies based on EEG involve the extraction of different spectra from EEG signals. Traditional methods of extracting these brainwaves (commonly δ, θ, α, β, γ) from EEG signals, like impulse-response filtering or wavelet decomposition, are computationally inefficient or unsuitable for real-time implementation. The Maximum-Mean-Minimum (MaMeMi) filter is a signal processing algorithm that is computationally efficient for signal filtering. The response of the MaMeMi filter is dependent on pre-decided filter coefficients. An obstacle to its implementation is that the filter coefficients have to be tuned to the sampling frequency. We propose the Modified-MaMeMi (MoMaMeMi) filter, in which the choice of coefficients is independent from the sampling frequency. Furthermore, we develop a band-pass MoMaMeMi filter which is duplicated in a filter bank, to decompose EEG signals into five common brainwaves. We validate the efficiency of the proposed filter bank by the increase in Signal-to-Noise Ratio (SNR). The maximum average increase in SNR is 19.68 dB. To prove utility of the filter-bank, we statistically compare the values of windowed average power extracted from the MoMaMeMi-filtered signals, between seizure and non-seizure components of the EEG data-set. A significant difference between the distributions suggests utility for classification problems. Since EEG-signal processing algorithms are highly customised and not limited to the 5 common brainwaves reported in this paper, we also develop a program to determine filter parameters for extraction of unique frequency bands in a bespoke MoMaMeMi filter.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Electroencephalography (EEG) is an important tool for characterizing the functioning of the brain. Studies based on EEG involve the extraction of different spectra from EEG signals. Traditional methods of extracting these brainwaves (commonly δ, θ, α, β, γ) from EEG signals, like impulse-response filtering or wavelet decomposition, are computationally inefficient or unsuitable for real-time implementation. The Maximum-Mean-Minimum (MaMeMi) filter is a signal processing algorithm that is computationally efficient for signal filtering. The response of the MaMeMi filter is dependent on pre-decided filter coefficients. An obstacle to its implementation is that the filter coefficients have to be tuned to the sampling frequency. We propose the Modified-MaMeMi (MoMaMeMi) filter, in which the choice of coefficients is independent from the sampling frequency. Furthermore, we develop a band-pass MoMaMeMi filter which is duplicated in a filter bank, to decompose EEG signals into five common brainwaves. We validate the efficiency of the proposed filter bank by the increase in Signal-to-Noise Ratio (SNR). The maximum average increase in SNR is 19.68 dB. To prove utility of the filter-bank, we statistically compare the values of windowed average power extracted from the MoMaMeMi-filtered signals, between seizure and non-seizure components of the EEG data-set. A significant difference between the distributions suggests utility for classification problems. Since EEG-signal processing algorithms are highly customised and not limited to the 5 common brainwaves reported in this paper, we also develop a program to determine filter parameters for extraction of unique frequency bands in a bespoke MoMaMeMi filter.
2020
Mittal, Rakshit; Baragi, Lalita; Mutnuri, Srikanth
Impact of Negative Factors and Importance of Monitoring Natural Wetland Ecosystems in Jharkhand: A Report on Biological Aspects Technical Report
2020.
Abstract | BibTeX | Altmetric | Dimensions | PlumX | Links:
@techreport{nokey,
title = {Impact of Negative Factors and Importance of Monitoring Natural Wetland Ecosystems in Jharkhand: A Report on Biological Aspects},
author = {Rakshit Mittal and Lalita Baragi and Srikanth Mutnuri},
url = {https://zenodo.org/records/4072324},
doi = {10.5281/ZENODO.4072323},
year = {2020},
date = {2020-07-10},
urldate = {2020-07-10},
abstract = {This book provides a detailed analysis of wetlands in Jharkhand over time. The report was commissioned by the State Government of Jharkhand to help frame policies around wetland conservation.},
keywords = {},
pubstate = {published},
tppubtype = {techreport}
}
This book provides a detailed analysis of wetlands in Jharkhand over time. The report was commissioned by the State Government of Jharkhand to help frame policies around wetland conservation.
Mittal, Rakshit; Banerjee, Rochisnu; Sarkar, Santonu; Bandyopadhyay, Soumyadip
Translation Validation of Loop involving Code Optimizing Transformations using Petri Net based Models of Programs Workshop
Proceedings of the International Workshop on Petri Nets and Software Engineering co-located with 41st International Conference on Application and Theory of Petri Nets and Concurrency (PETRI NETS 2020), CEUR Workshop Proceedings, Paris, France, 2020.
@workshop{nokey,
title = {Translation Validation of Loop involving Code Optimizing Transformations using Petri Net based Models of Programs},
author = {Rakshit Mittal and Rochisnu Banerjee and Santonu Sarkar and Soumyadip Bandyopadhyay},
editor = {Michael Köhler-Bussmeier and Ekkart Kindler and Heiko Rölke},
url = {https://www2.informatik.uni-hamburg.de/TGI/events/pnse20/pnse20-preview-add/paper9.pdf},
year = {2020},
date = {2020-06-24},
urldate = {2020-06-24},
booktitle = {Proceedings of the International Workshop on Petri Nets and Software Engineering co-located with 41st International Conference on Application and Theory of Petri Nets and Concurrency (PETRI NETS 2020)},
publisher = {CEUR Workshop Proceedings},
address = {Paris, France},
abstract = {Translation validation is the process of proving semantic equivalence between source and source-translation, ie, checking the semantic equivalence between the target code (which is a translation of the source program being compiled) and the source code. In this paper, we propose a translation validation technique for Petri net based models of programs which verify several code optimizing transformations involving loop. These types of transformation have been used in several application domains such as scheduling phase of High level synthesis, high performance computations etc. Our Petri net based equivalence checker checks the computational equivalence between two one-safe colour Petri nets. In this work, we have taken two versions of CPNs one corresponds to the source program and the other, the target programs. Using path based analysis technique, we have developed a sound method for proving several code optimizing transformations involving loop. We have also compared our results with other Petri net based equivalence checkers. The experimental result shows the efficacy of the method.},
keywords = {},
pubstate = {published},
tppubtype = {workshop}
}
Translation validation is the process of proving semantic equivalence between source and source-translation, ie, checking the semantic equivalence between the target code (which is a translation of the source program being compiled) and the source code. In this paper, we propose a translation validation technique for Petri net based models of programs which verify several code optimizing transformations involving loop. These types of transformation have been used in several application domains such as scheduling phase of High level synthesis, high performance computations etc. Our Petri net based equivalence checker checks the computational equivalence between two one-safe colour Petri nets. In this work, we have taken two versions of CPNs one corresponds to the source program and the other, the target programs. Using path based analysis technique, we have developed a sound method for proving several code optimizing transformations involving loop. We have also compared our results with other Petri net based equivalence checkers. The experimental result shows the efficacy of the method.
2019
Al-Ali, Rima; Amrani, Moussa; Bandyopadhyay, Soumyadip; Barisic, Ankica; Barros, Fernando; Blouin, Dominique; Erata, Ferhat; Giese, Holger; Iacono, Mauro; Klikovits, Stefan; Mittal, Rakshit; Navarro, Eva; Pelliccione, Patrizio; Taveter, Kuldar; Tekinerdogan, Bedir; Vanherpen, Ken
Framework to Relate/Combine Modeling Languages and Techniques Technical Report
2019.
Abstract | BibTeX | Altmetric | Dimensions | PlumX | Links:
@techreport{10.5281/zenodo.2527576,
title = {Framework to Relate/Combine Modeling Languages and Techniques},
author = {Rima Al-Ali and Moussa Amrani and Soumyadip Bandyopadhyay and Ankica Barisic and Fernando Barros and Dominique Blouin and Ferhat Erata and Holger Giese and Mauro Iacono and Stefan Klikovits and Rakshit Mittal and Eva Navarro and Patrizio Pelliccione and Kuldar Taveter and Bedir Tekinerdogan and Ken Vanherpen},
doi = {10.5281/zenodo.2527576},
year = {2019},
date = {2019-01-07},
urldate = {2019-01-07},
abstract = {This document reports on the Framework to Relate / Combine Modeling Languages and Techniques of Working Group1 on Foundations of the ICT COST Action IC1404 Multi-Paradigm Modelling for Cyber-Physical Systems (MPM4CPS). It first presents an ontology of Cyber Physical Systems in chapter 2 and then an ontology of Multi-Paradigm Modeling in chapter 3. Then, these ontologies are combined to define an ontology of Multi-Paradigm Modeling for Cyber Physical Systems presented in chapter 4. Finally, a number of megamodel examples are presented in chapter 6 that instantiate the core ontologies and make use of the catalog of languages and tools individuals.},
howpublished = {Zenodo},
keywords = {},
pubstate = {published},
tppubtype = {techreport}
}
This document reports on the Framework to Relate / Combine Modeling Languages and Techniques of Working Group1 on Foundations of the ICT COST Action IC1404 Multi-Paradigm Modelling for Cyber-Physical Systems (MPM4CPS). It first presents an ontology of Cyber Physical Systems in chapter 2 and then an ontology of Multi-Paradigm Modeling in chapter 3. Then, these ontologies are combined to define an ontology of Multi-Paradigm Modeling for Cyber Physical Systems presented in chapter 4. Finally, a number of megamodel examples are presented in chapter 6 that instantiate the core ontologies and make use of the catalog of languages and tools individuals.